1 white electronic designs corporation ? phoenix, az ? (602) 437-1520 hi-reliability product risc microprocessor module preliminary* may 2000 rev. 7 fig. 1 multi-chip package diagram overview the wedc 750/ssram module is targeted for high performance, space sensitive, low power systems and supports the following power management features: doze, nap, sleep and dynamic power management. the WED3C750A8M-200BX multi-chip package consists of: ? 750 risc processor ? dedicated 1mb ssram l2 cache, configured as 128kx72 ? 21mmx25mm, 255 ceramic ball grid array (cbga) ? maximum core frequency = 200mhz ? maximum l2 cache frequency = 100mhz ? maximum 60x bus frequency = 66mhz the WED3C750A8M-200BX is offered in industrial (-40 c to +85 c) and military (-55 c to +125 c) temperature ranges and is well suited for embedded applications such as missiles, aerospace, flight computers, fire control systems and rugged critical systems. * this data sheet describes a product under development, not fully characterized, and is subject to change without notice. ssram ssram m p 750 WED3C750A8M-200BX
2 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WED3C750A8M-200BX fig. 2 block diagram control unit instruction fetch branch unit completion system unit dispatch bht/btic 32k icache fxu1 fxu2 gprs rename buffers rename buffers lsu fprs fpu 32k dcache l2tags l2 cache biu 60x biu ssram ssram l2 cache bus 60x bus
3 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WED3C750A8M-200BX fig. 3 block diagram, l2 interconnect l2pin_data l2pin_data l2pin_data l2pin_data l2 clk_out a l2we l2ce a2-16 a0 a1 l2clk_out b l2pin_data l2pin_data l2pin_data l2pin_ data l2zz m p 750 dqa dqb dqc dqd k sgw se1 sa0 sa1 sa2-16 sa2-16 sa0 sa1 sgw se1 k dqa dqb dqc dqd ssram 1 ssram 2 ft sbd sbc sbb sba sw adsp adv se2 adsc se3 lbo g ft sbd sbc sbb sba sw adsp adv se2 adsc se3 lbo g 0vdd 0vdd l2dp0-3 dp0-3 l2dp4-7 dp0-3 zz zz
4 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WED3C750A8M-200BX fig. 4 pin assignments ball assignments of the 255 cbga package as viewed from the top surface. 1 2345678 910 11 12 13 14 15 16 a b c d e f g h j k l m n p r t substrate assembly underfill encapsulant die view side profile of the cbga package to indicate the direction of the top surface view.
5 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WED3C750A8M-200BX signal name pin number active i/o a[0-31] c16, e4, d13, f2, d14, g1, d15, e2, d16, d4, e13, g2, e15, h1, e16, h2, f13, j1, f14, j2, f15, h3, high i/o f16, f4, g13, k1, g15, k2, h16, m1, j15, p1 aack l2 low input abb k4 low i/o ap[0-3] c1, b4, b3, b2 high i/o artry j4 low i/o avdd a10 bg l1 low input br b6 low output ci e1 low output ckstp_in d8 low input ckstp_out a6 low ouput clk_out d7 output dbb j14 low i/o dbg n1 low input dbdis h15 low input dbwo g4 low input dh[0-31] p14, t16, r15, t15, r13, r12, p11, n11, r11, t12, t11, r10, p9, n9, t10, r9, t9, p8, n8, r8, t8, n7, high i/o r7, t7, p6, n6, r6, t6, r5, n5, t5, t4 dl[0-31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, high i/o n10, p13, n12, t13, p3, n3, n4, r3, t1, t2, p4, t3, r4 dp[0-7] m2, l3, n2, l4, r1, p2, m4, r2 high i/o drtry g16 low input gbl f1 low i/o gnd c5, c12, e3, e6, e8, e9, e11, e14, f5, f7, f10, f12, g6, g8, g9, g11, h5, h7, h10, h12, j5, j7, j10, j12, k6, k8, k9, k11, l5, l7, l10, l12, m3, m6, m8, m9, m11, m14, p5, p12 hreset a7 low input int b15 low input l1_tstclk (1) d11 high input l2_tstclk (1) d12 high input lssd_mode (1) b10 low input mcp c13 low input nc (no-connect) b7, b8, c3, c6, c8, d5, d6, h4, j16, a4, a5, a2, a3, b1, b5 ovdd (2) c7, e5, e7, e10, e12, g3, g5, g12, g14, k3, k5, k12, k14, m5, m7, m10, m12, p7, p10 pll_cfg[0-3] a8, b9, a9, d9 high input qack d3 low input qreq j3 low output rsrv d1 low output smi a16 low input sreset b14 low input sysclk c9 input ta h14 low input tben c2 high input tbst a14 low i/o package pinout listing
6 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WED3C750A8M-200BX characteristic symbol value unit core supply voltage vdd -0.3 to 2.75 v pll supply voltage avdd -0.3 to 2.75 v 60x bus supply voltage ovdd -0.3 to 3.6 v input supply vin -0.3 to 3.6 v storage temperature range tstg -55 to 150 c notes: 1. functional and tested operating conditions are given in operating conditions table. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution: vin must not exceed ovdd by more than 0.3v at any time including during power-on reset. 3. caution: ovdd must not exceed vdd/avdd by more than 1.2 v at any time including during power-on reset. 4. caution: vdd/avdd must not exceed ovdd by more than 0.4 v at any time including during power-on reset. 5. l2 avdd is internally tied to avdd. l2 ovdd is internally tied to ovdd. absolute maximum ratings recommended operating conditions characteristic symbol value unit core supply voltage vdd 2.5 to 2.7 v pll supply voltage avdd 2.5 to 2.7 v 60x bus supply voltage ovdd 3.135 to 3.465 v input supply vin gnd to ovdd v ambient temperature (mil) t a -55 to +125 c ambient temperature (ind) t a -40 to +85 c note: these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed package pinout listing (continued) signal name pin number active i/o tck c11 high input tdi a11 high input tdo a12 high output tea h13 low input tlbisync c4 low input tms b11 high input trst c10 low input ts j13 low i/o tsiz[0-2] a13, d10, b12 high output tt[0-4] b13, a15, b16, c14, c15 high i/o wt d2 low output vdd (2) f6, f8, f9, f11, g7, g10, h6, h8, h9, h11, j6, j8, j9, j11, k7, k10, l6, l8, l9, l11 voltdetgnd (3) f3 low output notes: 1. these are test signals for factory use only and must be pulled up to ovdd for normal machine operation. 2. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. 3. internally tied to gnd in the bga package to indicate to the power supply that a low-voltage processor is present.
7 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WED3C750A8M-200BX power consumption vdd=avdd=2.5 0.1v vdc, ovdd=3.3 5% vdc, gnd=0 vdc, 0 tj<105 c processor (cpu) frequency/l2 frequency 200 mhz/100mhz unit notes full-on mode typical 5.2 w 1,3 maximum 8.5 w 1, 2 doze mode maximum 2.1 w 1, 2 nap mode maximum 700 mw 1, 2 sleep mode maximum 750 mw 1, 2 sleep modeCpll and dll disabled maximum 100 mw 1, 2 notes: 1. these values apply for all valid 60x bus and l2 bus ratios. the values do not include ovdd. ovdd power is system dependent, but is typically <10% of vdd power. worst case power consumption, for avdd=35 mw. 2. maximum power is measured at vdd=2.625 v using a worst-case instruction mix. 3. typical power is an average value measured at vdd=avdd=2.5v, ovdd=3.3v in a system, executing typical applications and bench mark sequences. l2 cache control register (l2cr) the l2 cache control register, shown in figure 5, is a supervisor-level, implementation-specific spr used to configure and oper ate the l2 cache. it is cleared by hard reset or power-on reset. fig. 5 l2 cache control register (l2cr) the l2cr bits are described in table 1. l2e l2siz l2clk l2ram l2i l2oh 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 6 7 8 9 10111213141516171819 3031 l2wt l2df l2pe l2dr l2ctl l2ts l2sl l2byp l2ip reserved table1: l2cr bit settings bit name function 0 l2e l2 enable. enables l2 cache operation (including snooping) starting with the next transaction the l2 cache unit receives. b efore enabling the l2 cache, the l2 clock must be configured through l2cr[2clk], and the l2 dll must stabilize. all other l2cr bits m ust be set appropriately. the l2 cache may need to be invalidated globally. 1 l2pe l2 data parity generation and checking enable. enables parity generation and checking for the l2 data ram interface. when disabled, generated parity is always zeros. l2 parity is supported by wedc's WED3C750A8M-200BX, but is dependent on application. 2C3 l2siz l2 sizeshould be set according to the size of the l2 data rams used. 11 1 mbyte - setting for WED3C750A8M-200BX 4C6 l2clk l2 clock ratio (core-to-l2 frequency divider). specifies the clock divider ratio based from the core clock frequency th at the l2 data ram interface is to operate at. when these bits are cleared, the l2 clock is stopped and the on-chip dll for the l2 interface i s disabled. for nonzero values, the processor generates the l2 clock and the on-chip dll is enabled. after the l2 clock ratio is chosen, the dll must stabilize before the l2 interface can be enabled. the resulting l2 clock frequency cannot be slower than the clock frequency of the 60x bus interface. 000 l2 clock and dll disabled 001 ? 1 010 ? 1.5 011 reserved 100 ? 2 - setting for WED3C750A8M-200BX 101 ? 2.5 110 ? 3 111 reserved
8 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WED3C750A8M-200BX bit name function 7C8 l2ram l2 ram typeconfigures the l2 ram interface for the type of synchronous srams used: ? pipelined (register-register) synchronous burst srams that clock addresses in and clock data out the 750 does not burst data into the l2 cache, it generates an address for each access. 10 pipelined (register-register) synchronous burst sram - setting for WED3C750A8M-200BX 9 l2do l2 data-only. setting this bit enables data-only operation in the l2 cache. for this operation, only transactions from the l1 data cache can be cached in the l2 cache, which treats all transactions from the l1 instruction cache as cache-inhibited (bypass l2 cache, no l2 checking done). l2 data-only depends on application. 10 l2i l2 global invalidate. setting l2i invalidates the l2 cache globally by clearing the l2 bits including status bits. this bi t must not be set while the l2 cache is enabled. see motorola's user manual for l2 invalidation procedure. 11 l2ctl l2 ram control (zz enable). setting l2ctl enables the automatic operation of the l2zz (low-power mode) signal for cache rams. sleep mode is supported by the WED3C750A8M-200BX. while l2ctl is asserted, l2zz asserts automatically when the device enters nap or sleep mode and negates automatically when the device exits nap or sleep mode. this bit should not be set when the device is in nap mode and snooping is to be performed through deassertion of qack. 12 l2wt l2 write-through. setting l2wt selects write-through mode (rather than the default write-back mode) so all writes to the l2 cache also write through to the 60x bus. for these writes, the l2 cache entry is always marked as clean (valid unmodified) rather tha n dirty (valid modified). this bit must never be asserted after the l2 cache has been enabled as previously-modified lines can get rema rked as clean during normal operation. 13 l2ts l2 test support. setting l2ts causes cache block pushes from the l1 data cache that result from dcbf and dcbst instructions to be written only into the l2 cache and marked valid, rather than being written only to the 60x bus and marked invalid in the l2 cac he in case of hit. this bit allows a dcbz / dcbf instruction sequence to be used with the l1 cache enabled to easily initialize the l2 cache with any address and data information. this bit also keeps dcbz instructions from being broadcast on the 60x and single-beat cacheable store misses in the l2 from being written to the 60x bus. 0: setting for the l2 test support as this bit is reserved for tests. 14C15 l2oh l2 output hold. these bits configure output hold time for address, data, and control signals driven to the l2 data ram s. 00 0.5 ns - setting for WED3C750A8M-200BX 16 l2sl l2 dll slow. setting l2sl increases the delay of each tap of the dll delay line. it is intended to increase the delay thr ough the dll to accommodate slower l2 ram bus frequencies. 1: setting for WED3C750A8M-200BX because l2 ram interface is operated below 110 mhz. 17 l2df l2 differential clock. this mode supports the differential clock requirements of late-write srams. 0: setting for WED3C750A8M-200BX ' because late-write srams are not used. 18 l2byp l2 dll bypass is reserved. 0: setting for WED3C750A8M-200BX 19C30 reserved. these bits are implemented but not used; keep at 0 for future compatibility. 31 l2ip l2 global invalidate in progress (read only)see the motorola user's manual for l2 invalidation procedure. table1:l2cr bit settings (continued)
9 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WED3C750A8M-200BX package dimensions 255 ball grid array package description package outline 21x25mm interconnects 255 (16x16 ball array less one) pitch 1.27mm maximum module height 3.90mm ball diameter 0.8mm 0.006 (0.152) ? 3.14 (0.124) max 12345678910111213141516 a b c d e f g h j k l m n p r t ? 0.80 (0.032) bsc 1.27 (0.050) bsc 0.975 (0.038) ref 2.975 (0.117) ref a1 cor ner notes: 1. dimensions in millimeters and paranthetically in inches. 2. a1 corner is designated with a ball missing the array. 0.64 0.070 (0.025 0.003) 25.25 (0.994) max 19.05 (0.750) bsc 21.21 (0.835) max 19.05 (0.750) bsc
10 white electronic designs corporation ? phoenix, az ? (602) 437-1520 WED3C750A8M-200BX device grade: i = industrial -40 c to +85 c m = military screened -55 c to +125 c package type: b = 255 ceramic ball grid array c = 255 ceramic column grid array* core frequency (mhz) l2 cache density: 8mbits = 128k x 72 ssram powerpca: type 750a c = mcm-c 3 = powerpca white electronic designs corp. ordering information wed 3 c 750a 8m 200 x x powerpca is a trademark of international business machine corp. * advanced package, contact factory for availability.
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